The disclosed invention relates to the provision of conductive paths between devices and a metallization layer or between metallization layers of integrated circuits, and is more particularly directed to the formation of electrically conductive plugs for interconnecting devices and metallization layers of integrated circuits.
In an integrated circuit, the devices or elements formed in the substrate are interconnected with metallic (e.g., aluminum) leads which are typically formed by the sequential processes of masking and deposition. The processes of masking and deposition shall be referred to as metallization, and generally provides for a layer of metallization on top of a layer of insulating oxide or glass. The insulating oxide or glass on which the metallization is deposited generally includes openings or windows for the formation of (a) metallized contacts to silicon or polysilicon, or (b) metallized vias to another layer of metallization.
With known metallization techniques, however, the contact and via openings or windows must be selectively located for two and three layer metallization. Such selectivity is required due to photolithographic and deposition processing limitations.
Known metallization techniques include planarized and non-planarized processing. As used herein, planarizing refers to smoothing the surface of an insulating layer prior to deposition of metal. The planarized surface may comprise a substantially continuous planar surface, or may include planar areas of different levels. In any event, the top surfaces of the insulating layer are smoothed.
Specifically, with non-planarized processing, only one opening over a given region is allowed. In other words, only one layer is allowed to have an opening over a given region. Moreover, openings have to be at least a predetermined distance from another opening. The actual distance depends on whether an adjacent opening is in the immediately adjacent oxide layer.
With planarized processing, the limitations are not as stringent. More than one opening over a given region is allowed so long as the openings are not on adjacent oxide layers. However, due to processing limitations, the tops of the deposited metal over the openings include indentations and minimum spacing between adjacent openings is required. Such spacing requirements are less stringent than for non-planarized processing.
As a result of the design rules associated with known non-planarized and planarized processing of metallization layers, routing is necessarily complex and difficult. Further, such design rules limit device density, although greater desity is achieved with planarized processing as compared to non-planarized processing.
A further consideration with known processing of metallized contacts and vias is the limitation on minimum size of the openings. Specifically, if the openings are made too small, the deposited metallization at the edges of the openings will be too thin and may crack. The limitation on minimum opening size also affects device density.